specifications of any and all sanyo semiconductor co.,l td. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' sproductsor equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general el ectronics equipment (home appliances, av equipment, communication device, office equipment, industrial equ ipment etc.). the products mentioned herein shall not be intended for use for any "special application" (medica l equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, t ransportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of re liability and can directly threaten human lives in case of failure or malfunction of the product or may cause har m to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for app lications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. if there is n o consultation or inquiry before the intended use, our customer shall be solely responsible for the use. o3107 ms pc 20070827-s00002 no.a0919-1/8 LV8095LQ overview the LV8095LQ is a constant current driver ic for voice coil motors. it supports i 2 c control and integrates a digital/analog converter (dac). its ultraminiature package makes the ic ideal for constant-current driving the voice coil motors (af and zm) used in a wide variety of portable equipment including camera cell-phones. features ? constant current driver for voice coil motors. ? constant current control enabled by dac (8 bits). ? i 2 c bus control supported. ? wide operating voltage range (2.5 to 5.5v). ? no external capacitors needed (capacitor-less). ? ultraminiature package (uslp8 : 2.0 1.3 0.56mm) for easy soldering. ? built-in thermal protection circuit. ? built-in voltage drop protection circuit. specifications absolute maximum ratings at ta = 25 c parameter symbol conditions ratings unit maximum supply voltage v cc max -0.3 to +5.5 v maximum vdd voltage v dd max -0.3 to +5.5 v output voltage v out max out1 -0.3 to +6.0 v input voltage v in max scl, sda, pd -0.3 to +5.5 v gnd pin source current i gnd 200 ma allowable power dissipation pd max *mounted on a specified board. 650 mw operating temperature topr -30 to +85 c storage temperature tstg -40 to +150 c * specified board : 50mm 40mm 0.8mm, 4-layer glass epoxy circuit board. bi-cmos ic for vcms constant-current driver ic orderin g numbe r : ena0919
LV8095LQ no.a0919-2/8 allowable operating conditions at ta = 25 c parameter symbol conditions ratings unit supply voltage v cc 2.5 to 5.0 v v dd voltage v dd 1.3 to 5.0 v maximum preset output current i o 200 ma high-level input voltage v ih 0.8 v dd to v dd v low-level input voltage v il applied to scl, sda, and pd pins -0.3 to 0.2 v dd v electrical characteristics ta = 25 c, v cc = 2.8v, v dd = 2.8v ratings parameter symbol conditions min typ max unit i cco pd = 0v 0.1 1 a supply current i cc 1 pd = 2.8v 0.5 3 ma input current i in v in = 2.8v, vena = 2.8v -1 0 1 a vsat1 sw : on, sw : b, full code setting, i out = 50ma 0.10 0.18 v output saturation voltage vsat2 sw : on, sw : b, full code setting, i out = 100ma 0.20 0.4 v dac block resolution rf = 1 ? , sw1 : off, sw2 : a 8 bits relative accuracy inl rf = 1 ? , sw1 : off, sw2 : a 1 lsb differential linearity dnl rf = 1 ? , sw1 : off, sw2 : a 1 lsb full code current ifull rf = 1 ? , sw1 : off, sw2 : a 95 100 105 ma error code current 0 izero rf = 1 ? , sw1 : off, sw2 : a 1 4 ma spark killer diode reverse current is (leak) 1 a forward voltage vsf i out = 200ma * 1.3 v *1 : design guaranteed value (no measurement is performed) package dimensions unit : mm (typ) 3348 sanyo : uslp8(1.3x2.0) 1 8 2 (0.18) (0.65) 1.3 (0.25) 0.5 2.0 0.25 0.3 top view side view side view bottom view 0.6max 0.0nom 2 1 0.14 pd max -- ta ambient temperature, ta ? c allowable power dissipation, pd max ? w 0 0.7 0.6 0.65 0.34 0.4 0.5 0.2 0.3 0.1 0.8 ? 30 ? 20 80 60 20 40 010 0 specified board : 50.0 40.0 0.8mm 3 4-layer glass epoxy (2s2p)
LV8095LQ no.a0919-3/8 pin assignment *1 : the voltage applied to the v dd pin must be set to the same level as those of the sda, scl and pd input high-level voltages. *2 : setting the pd pin to low level powers down and resets the ic. set this pin temporarily to low level, then to high level after power-on, and keep it to high level (same voltage level as v dd ) during normal operation. block diagram wiring resistance (thick line) around the rf is added to the resistance of rf as an error. it must be kept as small as possible. formula for calculating constant current : i out = 0.1 rf if, for instance, i out is to be set to 100ma max : rf = 0.1 (100ma) rf = 1 ? notes on use ? determine the preset current value using the resistor between rfg and gnd accordi ng to the formula above. ? the recommended rf value is 1 ? . pin no. pin name pin description 1 gnd ground 2 rfg current sensing resistor connection 3 out output pin 4 v cc analog system power supply 5 v dd logic system power supply *1 6 sda i 2 c sda input 7 scl i 2 c scl input 8 pd power-down & reset *2 8 pd 7 scl uslp8 (top view) 6 sda 5 v dd 1 gnd 2 rfg 3 out 4 v cc i 2 c if c p u i 2 c decode gnd v cc 0.1 f sda v dd scl pd rf rfg out vcm 1 ? dac 8 bits current setting reference voltage voltage drop protection & thermal protection - +
LV8095LQ no.a0919-4/8 pin description pin no. pin name description equivalent circuit 1 gnd ground pin 2 3 rfg out 2 : rfg current detection resistor connection pin the current detection resistor (1 ? ) is connected between this pin and gnd to detect th e output current and perform constant current control. 3 : out output pin this is an nmos open drain output, and the voice coil motor is connected between this pin and the v cc pin for use. v cc 2 3 1k ? 4 5 v cc v dd 4 : v cc power supply input pin 5 : v dd this is separate from the v cc power supply pin for the sda, scl and pd logic input, and it is used while the same voltage as that for the high level of these logic input is applied to it. 6 sda i 2 c serial data input pin input high level : 0.8 v dd or higher input low level : 0.2 v dd or lower 1k ? v dd gnd 6 7 8 scl pd 7 : scl i 2 c serial clock input pin 8 : pd power down and reset when low, power-down and reset is performed at the same time. this pin is held high for normal use. in normal operation, however, this pin must be set low temporarily and an initial reset must be applied after v cc starts up. input high level : 0.8 v dd or higher input low level : 0.2 v dd or lower 1k ? v dd gnd 7 8
LV8095LQ no.a0919-5/8 serial bus communication specifications i 2 c serial transfer timing conditions standard mode standard mode parameter symbol conditions min typ max unit scl clock frequency fscl scl clock frequency 0 100 khz ts1 setup time of scl with respect to the falling edge of sda 4.7 s ts2 setup time of sda with respect to the rising edge of scl 250 ns data setup time ts3 setup time of scl with respect to the rising edge of sda 4.0 s th1 hold time of scl with respect to the rising edge of sda 4.0 s data hold time th2 hold time of sda with respect to the falling edge of scl 0 s twl scl low period pulse width 4.7 s pulse width twh scl high period pulse width 4.0 s ton scl, sda (input) rising time 1000 ns input waveform conditions tof scl, sda (input) falling time 300 ns bus free time tbuf interval between stop condition and start condition 4.7 s high-speed mode parameter symbol conditions min typ max unit scl clock frequency fscl scl clock frequency 0 400 khz ts1 setup time of scl with respect to the falling edge of sda 0.6 s ts2 setup time of sda with respect to the rising edge of scl 100 ns data setup time ts3 setup time of scl with respect to the rising edge of sda 0.6 s th1 hold time of scl with respect to the rising edge of sda 0.6 s data hold time th2 hold time of sda with respect to the falling edge of scl 0 s twl scl low period pulse width 1.3 s pulse width twh scl high period pulse width 0.6 s ton scl, sda (input) rising time 300 ns input waveform conditions tof scl, sda (input) falling time 300 ns bus free time tbuf interval between stop condition and start condition 1.3 s th1 ton ts2 th2 twh twl sda scl start condition input waveform condition stop condition ts1 ts3 th1 resend start condition tbuf tof
LV8095LQ no.a0919-6/8 i 2 c bus transmission method start and stop conditions the i 2 c bus requires that the state of sda be preserved while scl is high as shown in the timing diagram below during a data transfer operation. when data is not being transferred, both scl and sda are in the high state. the start condition is generated and access is started when sda is changed from high to low while scl and sda are high. conversely, the stop condition is generated and access is e nded when sda is changed from low to high while scl is high. data transfer and acknowledgement response after the start condition has been generated, the data is tr ansferred one byte (8 bits) at a time. generally, in an i 2 c bus, a unique 7-bit slave address is assigned to each device, and the firs t byte of the transfer data is allocated to the 7-bit slave address and to the command (r/w) indicating the transfer direction of the subsequent data. however, this ic is provided with only a write mode for receiving the da ta. every time 8 bits of da ta for each byte are transf erred, the ack signal is sent from the receiving end to the sending end. immediately after the clock pulse of scl bit 8 in the data transferred has fallen to low, sda at the sending end is re leased, and sda is set to low at the recei ving end, causing the ack signal to be sent. when, after the receiving end has sent the ack signal, the transfer of the next byte re mains in the receiving status, the receiving end releases sda at the falling edge of the ninth scl clock. ts2 th2 scl sda m s b l s b a c k l s b a c k m s b m s b l s b a c k w data x : don't care a1 scl sda (write) data slave address 2nd byte 3ed byte 1st byte start stop a2 a3 a4 a5 a6 a7 0 pd x d7d6d5d4d3d2 d1 d0xxxxxx th1 ts3 scl sda start condition stop condition
LV8095LQ no.a0919-7/8 the standard data transfer to this device consists of three by tes : the slave address of the first byte and the data of the second and third bytes. the table below shows the format of the second and third bytes. 2nd byte 3rd byte serial data bits sd7 sd6 sd5 sd4 sd3 s d2 sd1 sd0 sd7 sd6 sd5 sd4 sd3 sd2 sd1 sd0 function pd d7 d6 d5 d4 d3 d2 d1 d0 slave address : 0110011(0) pd : power-down d1-d7 : 8-bit data used to set output constant current ; min = 00000000, max = 11111111 d0-d7 setting method (output current design values assume an rf of 1 ? ) current setting code d7 d6 d5 d4 d3 d2 d1 output setting (lsb) output current (ma) (design value) 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0.392 2 0 0 0 0 0 1 0 2 0.784 254 1 1 1 1 1 1 0 254 99.608 255 1 1 1 1 1 1 1 255 100 specified test circuit pd scl sda v dd 876 aaa 5 1234 gnd rfg out v cc a a v b 1 ? 15 ? a sw2 sw1 1 f 1 f
LV8095LQ ps no.a0919-8/8 sanyo semiconductor co.,ltd. assumes no responsib ility for equipment failures that result from using products at values that exceed, even momentarily, rate d values (such as maximum ra tings, operating condition ranges, or other parameters) listed in products specif ications of any and all sanyo semiconductor co.,ltd. products described or contained herein. sanyo semiconductor co.,ltd. strives to supply high-qual ity high-reliability products, however, any and all semiconductor products fail or malfunction with some probabi lity. it is possible that these probabilistic failures or malfunction could give rise to acci dents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause dam age to other property. when designing equipment, adopt safety measures so that these kinds of accidents or e vents cannot occur. such measures include but are not limited to protective circuits and error prevention c ircuits for safe design, redundant design, and structural design. upon using the technical information or products descri bed herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable f or any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. information (including circuit diagr ams and circuit parameters) herein is for example only; it is not guaranteed for volume production. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equi pment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. in the event that any or all sanyo semiconductor c o.,ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities conc erned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any in formation storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd. this catalog provides information as of october, 2007. specifications and information herein are subject to change without notice.
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